The physical layout of a very-large scale integration (“VLSI”) design has to adhere to certain design rules. Typically a Design Rule Checking (DRC) tool is utilized to ensure that a given layout conforms to the set of design rules. The design rules, provided by the manufacturer and specific to a process node, are necessary to ensure the devices are manufacturable and can be produced at an appropriate yield. The design rules may be applicable to physical shapes or shapes that are derived from physical shapes using geometric operations. The shapes that are derived from physical shapes are said to reside on a derived layer and are referred to as derived layer shapes.
Oftentimes contemporary DRC tools do not provide enough information to allow for the visualization of a violation by a derived layer shapes because all that can be determined is textual description of a constraint that failed and which layers are involved in the violation. Typically, to repair the violation by using the textual description and which layers are involved is extremely time-consuming and error-prone, leading to a substantial loss in productivity and turnaround time when producing the design.
Accordingly, what is needed is a system and method to address the above identified issues. The system and method should be easily implemented, cost effective and adaptable to existing environments. The present invention addresses such a need.